Flat panel display is a display apparatus for displaying images based on pixel circuits; and for displaying images normally, various types of pixel circuits may need to be adopted with various types of driving circuit designs.
Referring to FIG. 1, which is a circuit view of a conventional pixel circuit used in a flat panel display. As shown, the pixel circuit 10 is configured to, while being supplied with operations voltage levels OVDD, VIN and OVSS, determine when to receive display data DATA and determine when to control a light emitting diode D1 to emit light by controlling P-type transistors T1, T2, T3, T4, T5 and T6 and two capacitors Cst1 and Cst2 through gate control signals Scan_N, Scan_N−1 and a light emitting control signal EM. For example, as shown in FIG. 1, the transistor T1 is configured to have its control terminal only electrically coupled to the gate control signal Scan_N−1; it first terminal only connected to the first terminal of the capacitors Cst1, the second terminal of the capacitors Cst2, the first terminal of the transistor T3 and the control terminal of the transistor T4; and its second terminal only electrically coupled to the operation voltage level VIN. The transistor T2 is configured to have its control terminal only connected to the light emitting control signal EM and the control terminal of the transistor T5; it first terminal only connected to the second terminal of the capacitors Cst1 and the operation voltage level OVDD; and its second terminal only connected to the first terminal of the transistor T4 and the first terminal of the transistor T6. The transistor T3 is configured to have its control terminal only connected to the first terminal of the capacitors Cst2, the control terminal of the transistor T6 and the gate control signal Scan_N; and it second terminal only connected to the second terminal of the transistor T4 and the first terminal of the transistor T5. The transistor T5 is configured to have its second terminal only connected to the first terminal of the light emitting diode D1. The light emitting diode D1 is configured to have its second terminal only connected to the operation voltage level OVSS. The transistor T6 is configured to have its second terminal only connected to the display data DATA. In response to the pixel circuit 10 of FIG. 1, currently a driving circuit of FIG. 2 is employed.
Referring to FIG. 2, which is a circuit block view of a conventional driving circuit used in a flat panel display. As shown, the flat panel display 20 includes a display area 200, in which a plurality of pixel circuits as illustrated in FIG. 1 are disposed. Each pixel circuit is controlled by the gate control signals Scan_N, Scan_N−1 and the light emitting control signal EM. In order to clarify the relationship between the control signals and the pixel circuits, the gate control signals supplied to the pixel circuit in the first row are provided by the first gate control signal generation unit Scan_P(1) and the second gate control signal generation unit Scan_P−1(1), respectively; and the light emitting control signal supplied to the pixel circuit in the first row is provided by the light emitting control signal generation unit EMP(1). Therefore, when the display area 200 has 960 rows of pixel circuit, accordingly there must exist 960 first gate control signal generation units Scan_P(1), Scan_P(2), . . . , Scan_P(959) and Scan_P(960), 960 second gate control signal generation units Scan_P−1(1), Scan_P−1(2), . . . , Scan_P−1(959) and Scan_P−1(960), and 960 light emitting control signal generating units EMP(1), EMP(2), . . . , EMP(959) and the EMP(960).
In a conventional driving circuit as shown in FIG. 2, the first gate control signal generation units Scan_P(1)˜Scan_P(960) and the second gate control signal generation units Scan_P−1(1)˜Scan_P−1(960) are disposed on the same side of the display area 200, and the light emitting control signal generating units EMP(1)˜EMP(960) are disposed on another side of the display area 200. Each one of the first gate control signal generation units Scan_P(1)˜Scan_P(960) and each one of the second gate control signal generation units Scan_P−1(1)˜Scan_P−1(960) are controlled by one of the shift registers RSR(1)˜RSR(960). For example, a pair of the first gate control signal generation unit Scan_P(1) and the second gate control signal generation unit Scan_P−1(1) are only controlled by the shift registers RSR(1); . . . ; and a pair of the first gate control signal generation unit Scan_P(960) and the second gate control signal generation unit Scan_P−1(960) are only controlled by the shift registers RSR(960). Similarly, each one of the light emitting control signal generation units EMP(1)˜EMP(960) is controlled by one of the shift registers LSR(1)˜LSR(960). For example, the light emitting control signal generation unit EMP(1) is only controlled by the shift register LSR(1); . . . ; and the light emitting control signal generation unit EMP(960) is only controlled by the shift register LSR(960). It is to be noted that the shift registers LSR(1)˜LSR(960) and the shift registers RSR(1)˜RSR(960) are different elements or different groups. In addition, to facilitate a less complicate design for clock signals, the driving circuit may further be disposed with dummy shift registers RBDSR, LUDSR and LBDSR. Specifically, the dummy shift register RBDSR is only connected to the last shift register RSR(960); the dummy shift register LUDSR is only connected to the first shift register LSR(1); and the dummy shift register LBDSR is only connected to the last shift register LSR(960).
Through the driving circuit of FIG. 2, the display panel 20 can display images normally. However, when the pixel circuits 10 of FIG. 1 are configured to display images through a driving of the driving circuit of FIG. 2, the gate control signals Scan_N, Scan_N−1 may have mismatch impedance issue, which may lead to a poor luminous uniformity on the display panel 20. In addition, conventionally, the shift registers, the first gate control signal generation unit and the second gate control signal generation unit may need a lot of transistors for an implementation; thus, once these transistors have electrical drifts caused by manufacturing process errors, these shift registers may not have normal functions and consequentially may result in display deterioration.